US 2026/0238522 A1 · DECISION FEEDBACK EQUALIZER WITH LOWER POWER CONSUMPTION AND HIGH SPEED

Abstract

The present invention provides an equalizer including a summer, a first processing circuit, a second processing circuit and a DAC. The summer is configured to combine an input signal with a feedback signal to generate a compensated input signal. The first processing circuit includes a first summer, a first slicer, a second summer and a second slicer. The first summer is configured to combine a first reference signal with a second signal to generate an adjusted first reference signal, for the first slicer to generate a first output signal. The second summer is configured to combine a second reference signal with the second signal to generate an adjusted second reference signal, for the second slicer to generate a second output signal. The second processing circuit receives the compensated signal to generate a third output signal and a fourth output signal, for the DAC to generate the second signal.

Claims18

Dependent claims

An equalizer, comprising:

a summer, configured to combine an input signal with a feedback signal to generate a compensated input signal;
a first processing circuit comprising:
a first summer, configured to combine a first reference signal with a second signal to generate an adjusted first reference signal;
a first slicer, configured to compare the compensated input signal with the adjusted first reference signal to generate a first output signal;
a second summer, configured to combine a second reference signal with the second signal to generate an adjusted second reference signal;
and
a second slicer, configured to compare the compensated input signal with the adjusted second reference signal to generate a second output signal;
a second processing circuit, configured to receive the compensated signal to generate a third output signal and a fourth output signal;
and
a digital-to-analog converter (DAC), configured to perform a digital-to-analog conversion operation on the third output signal and the fourth output signal to generate the second signal.

7 more elements

An equalizer, comprising:

a summer, configured to combine an input signal with a feedback signal to generate a compensated input signal;
a first processing circuit comprising:
a first summer, configured to combine a first reference signal with a second signal to generate an adjusted first reference signal;
a first slicer, configured to compare the compensated input signal with the adjusted first reference signal to generate a first output signal;
a second summer, configured to combine a second reference signal with the second signal to generate an adjusted second reference signal;
and
a second slicer, configured to compare the compensated input signal with the adjusted second reference signal to generate a second output signal;
a second processing circuit, configured to receive the compensated signal to generate a third output signal and a fourth output signal;
a third processing circuit, configured to receive the compensated signal to generate a fifth output signal and a sixth output signal;
a fourth processing circuit, configured to receive the compensated signal to generate a seventh output signal and an eighth output signal;
a digital-to-analog converter (DAC), configured to perform a digital-to-analog conversion operation on the seventh output signal and the eighth output signal.

8 more elements

Dependencies are inferred from the claim text.

Decision feedback equalizer with lower power consumption and high speed

Life of this patent

Decision feedback equalizer with lower power consumption and high speed

Life of this patent

Abstract

Claims18