Preserve ordering between posted, non-posted, and completion transactions
AssigneeIntel Corporation
InventorsShalini Sharma, Scott Constable, Raghunandan Makaram, Christopher Van Beek
Life of this patent
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AssigneeIntel Corporation
InventorsShalini Sharma, Scott Constable, Raghunandan Makaram, Christopher Van Beek
Estimating the term…
Systems, methods, and apparatuses to detect reordering issues are described. In some examples, a system comprises a first Peripheral Component Interconnect Express (PCIe) device to transmit transaction layer packets (TLPs) and integrity and data encryption sync (IDE_SYNC) messages to a second PCIe device; and the second PCIe device to receive the TLPs and IDE_SYNC messages, wherein the second PCIe device is to perform at least one of a detection of a TLP reordering by a PCIe fabric based at least in part on when an IDE_SYNC message is received and/or a detection of an TLP ordering error when a TLP is received before a IDE_SYNC message that preceded it.
A system comprising:
A method comprising:
Dependencies are inferred from the claim text.