Quasi-adiabatic circuits
AssigneeQAL Semiconductor, Inc.
InventorsJames Lupino, Tommy Allen Agan
Life of this patent
Estimating the term…
Abstract
Apparatus and associated methods relate to a quasi-adiabatic circuit that includes a plurality of quasi-adiabatic logic gates daisy-chain connected in a phased sequence. Each of the quasi-adiabatic logic gates in the daisy-chained sequence has power nodes conductively coupled to one of a phased sequence of sinusoidal power signals. The sinusoidal power signal conductively coupled to each of the quasi-adiabatic logic gates is phase delayed from that of the sinusoidal power signal conductively coupled to its immediately preceding quasi-adiabatic logic gate in the daisy-chained sequence. The phase delay is equal to 360° divided by the number of sinusoidal power signals in the phase sequence of sinusoidal power signals.
Claims20
A quasi-adiabatic logic circuit comprising:
- a sinusoidal power generating circuit configured to generate a plurality of sinusoidal power signals of a common frequency evenly phase distributed over 360° in a modulo phased sequence, each of the plurality of sinusoidal power signals having a phase lagging the phase of a previous one of the modulo phased sequence and leading the phase of a following one of the modulo phased sequence by a delta phase angle Δθ;
- and
- a plurality of quasi-adiabatic logic gates daisy-chain connected output-to-input, each of the plurality of quasi-adiabatic logic gates powered by a corresponding one of the plurality of sinusoidal power signals, each of the plurality of quasi-adiabatic logic gates including:
- one or more logic input terminals configured to receive one or more corresponding logic input signals;
- and
- a logic output terminal configured to provide a logic output signal, wherein the logic output signal is characterized by the phase of the corresponding one of the plurality of sinusoidal power signals providing power thereto.
A quasi-adiabatic logic circuit comprising:
- a clock generation circuit, configured to generate a plurality of clock signals phase-distributed over 360° in a modulo phased sequence, each respective one of the plurality of clock signals having a phase lagging a phase of a previous one of the modulo phased sequence and leading a phase of a following one of the modulo phased sequence;
- and
- a plurality of quasi-adiabatic logic gates respectively powered by corresponding ones of the plurality of clock signals.
A method for operating a quasi-adiabatic logic circuit, the method comprising:
- generating a plurality of clock signals phase-distributed over 360° in a modulo phased sequence, each respective one of the plurality of clock signals having a phase lagging a phase of a previous one of the modulo phased sequence and leading a phase of a following one of the modulo phased sequence;
- respectively powering a plurality of quasi-adiabatic logic gates using corresponding ones of the plurality of clock signals;
- and
- switching respective transistors within respective ones of the quasi-adiabatic logic gates when a drain-to-source bias voltage across the respective transistors is substantially zero.
Dependencies are inferred from the claim text.