Clock duty cycle monitoring and adjustment
AssigneeQUALCOMM Incorporated
InventorsFarrukh AQUIL, Boris Dimitrov ANDREEV, Patrick ISAKANIAN, Yong XU, Vishal MISHRA
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Abstract
Certain aspects of the disclosure relate to a memory device and a clock duty cycle adjuster (DCA) that is located after a clock divider to ensure that the duty cycle feedback can adjust the clock post-divider without affecting the divider's input clock. In some aspects, a duty cycle monitor (DCM) can be placed at the input clock to the divider to enable a host using a memory device to use its own DCA based on feedback from the DCM.
Claims20
A memory apparatus comprising:
- a clock divider configured to divide an input clock signal into an internal clock signal with a reduced frequency;
- a clock tree configured to distribute the internal clock signal to one or more internal components of the memory apparatus;
- and
- a first duty cycle adjuster (DCA) connected to the clock tree, the first DCA configured to adjust a clock timing of the internal clock signal based on a duty cycle feedback pertaining to the internal clock signal.
A method for controlling clock timing of a memory apparatus, comprising:
- dividing an input clock signal into an internal clock signal with a reduced frequency;
- distributing the internal clock signal to one or more internal components of the memory apparatus;
- and
- adjusting a clock timing of the internal clock signal based on a duty cycle feedback pertaining to the internal clock signal.
A memory apparatus, comprising:
- means for dividing an input clock signal into an internal clock signal with a reduced frequency;
- means for distributing the internal clock signal to one or more internal components of the memory apparatus;
- and
- means for adjusting a clock timing of the internal clock signal based on a duty cycle feedback pertaining to the internal clock signal.
Dependencies are inferred from the claim text.