US 2026/0238199 A1 · PARALLEL MONOTONIC SYNCHRONIZER

Abstract

Systems and methods are disclosed related to synchronizing a monotonic signal. A monotonic signal indicates an event at which the signal changes in only one direction (either rising or falling edges). The signal is restored before each event and the falling or rising edge to restore the signal may occur asynchronously. In at least one embodiment, an asynchronous signal generated in a first clock domain is sampled in a second clock domain by a plurality of flip-flops in parallel and the sampled signals output by the plurality of flip-flops are combined produce a synchronized signal in the second clock domain. The number of sampling flip-flops may be increased to reduce the probability of the combined output remaining metastable to an acceptable level. A monotonic synchronizer circuit may be used to construct a first-in first-out (FIFO) synchronizer.

Claims24

Dependent claims

A monotonic signal synchronizer circuit for producing an output signal in response to a monotonic signal that is synchronous with a rising edge or a falling edge of a first clock signal, the monotonic signal synchronizer circuit comprising:

a plurality of synchronizing flip-flops including at least two flip-flops that are each clocked by a second clock signal for directly sampling the monotonic signal at either a rising edge or a falling edge of the second clock signal to produce a sampled signal at an output of each of the at least two flip-flops;
logic for combining the sampled signals to produce a presence signal;
and
a second flip-flop circuit clocked by the second clock signal for sampling the presence signal at either a rising or falling edge of the second clock signal to produce an output signal.

1 more element

Dependencies are inferred from the claim text.

Parallel monotonic synchronizer

Life of this patent

Parallel monotonic synchronizer

Life of this patent

Abstract

Claims24