System of Free Running Oscillators for Digital System Clocking Immune to Process, Voltage and Temperature (PVT) Variations
AssigneeAlliacense Limited LLC
InventorVojin G. Oklobdzija
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Abstract
A system of free running oscillators synchronized to the lowest frequency running one and following PVT variation generates a system clock. A method is particularly applicable to clock relatively small clock domains within a multi-core chip containing thousands of cores, and where the clock domain encompasses one or more cores and additional logic blocks. The resulting system clock is divided by 2k using latches or flip-flops to achieve a symmetric 50-50 duty cycle of the system clock. Further, such PVT insensitive system clock can be used as a reference for a PLL or DLL generated clock for the domain.
Claims17
A system of free running oscillators whose frequency is determined by PVT, running in synchrony with each other providing a composite system clock.
An apparatus comprising:
- an integrated circuit substrate providing different circuit speeds depending on location on the substrate;
- an integrated circuit comprising a plurality of circuits formed in said integrated circuit substrate and spanning a defined area of said integrated circuit substrate;
- a plurality of ring oscillators formed in said defined area of said integrated circuit at different locations;
- said ring oscillators connected to each other;
- a clock distribution system connected to said plurality of circuits of said integrated circuit;
- and
- said plurality of ring oscillators connected to said clock distribution system.
Dependencies are inferred from the claim text.