Circuit and method for driving an inductive load with reduced power loss

An active circuit for driving an inductive load, the active circuit including a power output circuit and a control circuit;

• the power output circuit including:
• a first capacitor (C1) and a first diode (D1) that are connected in series across a positive terminal and a negative terminal of a load circuit that includes the inductive load;
• a second diode (D4) having an anode connected at a node between the first capacitor (C1) and the first diode (D1), and a cathode connected to a gate of a first transistor (M1);
• the first transistor (M1) having a drain connected to a gate of a second transistor (M2), and a gate connected to the negative terminal of the load circuit;
• the second transistor (M2) having a drain connected to the anode of the second diode (D4) and a source connected to a cathode of a clamping diode (D6);
• and
• the clamping diode (D6) having an anode connected to the gate of a third transistor (M3), which has a drain and a source connected to the positive terminal and negative terminal, respectively, of the load circuit;
• an active terminal (Pin 3) connected to an anode (AN11) of a third diode D11 and a cathode (CAT11) of the third diode D11 is connected to the gate (G3) of the third transistor (M3);
• and
• a disable terminal (Pin 5) connected to a cathode (CAT15) of the diode D15 and an anode (AN15) of the diode D15 is connected to the gate (G3) of the transistor (M3);
• the control circuit including:
• a constant voltage circuit connected to the gate of the third transistor (M3) and the negative terminal of the load circuit through an input diode (D7);
• an oscillator (U1) having an output connected to an inverting input terminal of a power modulator (U3);
• a voltage reference circuit (C7, R14, D8) connected to the negative terminal of the load circuit;
• and
• a comparator (U2) having a non-inverting input connected to the positive terminal of the load circuit and an inverting input connected to the voltage reference circuit (C7, R14, D8),
• wherein a load voltage across the positive and negative terminals of the load circuit, a first voltage to the active terminal, and the second diode (D4) enters a conducting state when the load circuit reaches a specified voltage less than the load voltage, which causes each of the first transistor (M1), the second transistor (M2), and the third transistor (M3) to enter a conducting state such that after a specified period the power output circuit shuts off;
• wherein when a voltage value at the non-inverting terminal of the comparator (U2) exceeds a voltage of the voltage reference circuit (C7, R14, D8), an output of the comparator is mixed with the output of the oscillator and causes the power modulator (U3) to provide an output voltage to the power output stage through the gate of the third transistor (M3) so that current flow through the load (L1) is increased and a magnetic field at the load (L1) is sustained, and
• wherein when a second voltage that is less than an output of the voltage reference circuit to the disable terminal, the control circuit is disabled and the active circuit is deactivated.

A method for driving an inductive load with an active circuit, the active circuit including a power output circuit and a control circuit;

• the power output circuit including:
• a first capacitor (C1) and a first diode (D1) that are connected in series across a positive terminal and a negative terminal of a load circuit that includes the inductive load;
• a second diode (D4) having an anode connected at a node between the first capacitor (C1) and the first diode (D1), and a cathode connected to a gate of a first transistor (M1);
• the first transistor (M1) having a drain connected to a gate of a second transistor (M2), and a gate connected to the negative terminal of the load circuit;
• the second transistor (M2) having a drain connected to the anode of the second diode (D4) and a source connected to a cathode of a clamping diode (D6);
• and
• the clamping diode (D6) having an anode connected to the gate of a third transistor (M3), which has a drain and a source connected to the positive terminal and negative terminal, respectively, of the load circuit;
• an active terminal (Pin 3) connected to an anode (AN11) of a third diode D11 and a cathode (CAT11) of the third diode D11 is connected to the gate (G3) of the third transistor (M3);
• and
• a disable terminal (Pin 5) connected to a cathode (CAT15) of the diode D15 and an anode (AN15) of the diode D15 is connected to the gate (G3) of the transistor (M3);
• the control circuit including:
• a constant voltage circuit connected to the gate of the third transistor (M3) and the negative terminal of the load circuit through an input diode (D7);
• an oscillator (U1) having an output connected to an inverting input terminal of a power modulator (U3);
• a voltage reference circuit (C7, R14, D8) connected to the negative terminal of the load circuit;
• and
• a comparator (U2) having a non-inverting input connected to the positive terminal of the load circuit and an inverting input connected to the voltage reference circuit (C7, R14, D8);
• and
• an active terminal (Pin 4) is connected to the inverting input (INV2) of the voltage comparator (U2) of the control circuit 404, the method comprising:
• applying a load voltage across the positive and negative terminals of the load circuit;
• applying a first voltage to the active terminal,
• wherein the second diode (D4) enters a conduct state when the load circuit reaches a specified voltage less than the load voltage, which causes each of the first transistor (M1), the second transistor (M2), and the third transistor (M3) to enter a conducting state such that after a specified period the power output circuit shuts off;
• and
• wherein when a voltage value at the non-inverting terminal of the comparator (U2) exceeds a voltage of the voltage reference circuit (C7, R14, D8), an output of the comparator is mixed with the output of the oscillator and causes the power modulator (U3) to provide an output voltage to the power output stage through the gate of the third transistor (M3) so that current flow through the load (L1) is increased and a magnetic field at the load (L1) is sustained,
• the method further comprising:
• applying a second voltage to the disable terminal to disable the control circuit and deactivate the active circuit, wherein the second voltage is less than the voltage reference circuit.