US 2026/0237452 A1Published application

In-memory computation device having an improved programming circuit and programming method

AssigneeSTMicroelectronics International N.V.

InventorsMarco PASOTTI, Riccardo ZURLA, Jacopo John BERTOLINI AGNOLETTO, Emanuela CALVETTI

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Abstract

An in-memory computation device for performing an in-memory computation operation has a programming circuit. The programming circuit maps a signed computational weight into a group of memory cells of the IMC device. The group of cells has a first set of cells and a second set of cells that are configured to provide, during the execution of the in-memory computation operation, current contributions as a function of their respective programming and having opposite signs to each other. The programming circuit programs a memory cell based on the computational weight, detects a programming error of the memory cell of the first set of cells, and programs a memory cell of the second set of cells to account for the detected programming error.

Claims18

Dependent claims

An in-memory computation (IMC) device configured to perform an in-memory computation operation, wherein the IMC device comprises:

a memory array including a group of memory cells configured to provide an overall current contribution during an execution of the in-memory computation operation;
the group of memory cells comprising a first set of memory cells configured to provide, during the execution of the in-memory computation operation, a first current contribution that is a function of a programming of the first set of memory cells, and a second set of memory cells configured to provide, during the execution of the in-memory computation operation, a second current contribution that is a function of a programming of the second set of memory cells, wherein the overall current contribution is a function of a difference between the first current contribution and the second current contribution;
and
a programming circuit configured to map a signed computational weight into the group of memory cells by operating to:
program at least one memory cell of the first set of memory cells at a first programming state based on the computational weight;
detect a programming error of the at least one memory cell of the first set of memory cells, wherein the programming error is indicative of an error between a target programming state of the at least one memory cell of the first set of memory cells and an actual programmed state of the at least one memory cell of the first set of memory cells;
and
program at least one memory cell of the second set of memory cells at a second programming state which includes a corrective value based on the programming error.

5 more elements

A method for mapping a signed computational weight into a group of memory cells of a memory array of an in-memory computation (IMC) device configured to perform an in-memory computation operation, wherein the group of memory cells is configured to provide an overall current contribution during the execution of the in-memory computation operation which is a function of the signed computational weight, and wherein the group of memory cells comprises a first set of memory cells configured to provide a first current contribution during the execution of the in-memory computation operation that is a function of the programming of the first set of memory cells, and a second set of memory cells configured to provide a second current contribution during the execution of the in-memory computation operation that is a function of the programming of the second set of memory cells, the overall current contribution being a function of a difference between the first current contribution and the second current contribution, the method comprising:

programming at least one memory cell of the first set of memory cells at a first programming state based on the computational weight;
detecting a programming error of the at least one memory cell of the first set of memory cells, the programming error being indicative of an error between a target programming state of the at least one memory cell of the first set of memory cells and an actual programmed state of the at least one memory cell of the first set of memory cells;
and
programming at least one memory cell of the second set of memory cells at a second programming state including a corrective value based on the programming error.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 19/534,028Filed 9 Feb 2026
Priority: IT 10202500000246310 Feb 2025
Published: 13 Aug 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification20 codes

G11C 29/52
Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation: protection of memory contents;…
G06F 7/5443
For evaluating functions by calculation: sum of products
G06F 17/16
Complex mathematical operations: matrix or vector computation , e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
G06N 3/063
Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons: using electronic means