Testing adapters, testing systems, and testing methods for memory apparatus

A testing system to test a memory apparatus, the testing system comprising:

• a testing adapter;
• and
• a host, wherein:
• the testing adapter comprises a first interface circuit, a second interface circuit, a third interface circuit, a fourth interface circuit, a first bridge chip, and a second bridge chip;
• the first interface circuit and the third interface circuit are configured to be connected to the host, the second interface circuit is configured to be connected to a debugging information interface circuit of the memory apparatus, and the fourth interface circuit is configured to be connected to a data interface circuit of the memory apparatus;
• the first bridge chip is configured to be connected to the first interface circuit and to the second interface circuit, and the second bridge chip is configured to be connected to the first interface circuit and to the fourth interface circuit;
• the host is configured to send a testing control instruction to the testing adapter;
• and
• the first bridge chip and the second bridge chip are configured to perform a testing operation on the memory apparatus based on the testing control instruction.

A method for testing a memory apparatus, the method comprising:

• receiving a testing control instruction from a host, the receiving of the testing control instruction includes:
• receiving the testing control instruction at a first bridge chip of a testing adapter, the first bridge chip connected to a first interface circuit and a second interface circuit of the testing adapter, the testing adapter including a third interface circuit connected to the host;
• and
• receiving the testing control instruction at a second bridge chip of the testing adapter, the second bridge chip connected to the first interface circuit and a fourth interface circuit of the testing adapter;
• and
• performing, by the first bridge chip and the second bridge chip, a testing operation on the memory apparatus based on the testing control instruction.