Efuse bit-cell in stacking structure

A memory device, comprising:

• a plurality of memory cells, each of the plurality of memory cells comprising an access transistor, a control gate transistor, a resistive element, a read select transistor, and a write select transistor;
• a plurality of word lines;
• a plurality of control gate lines;
• a plurality of bit lines;
• a plurality of read select lines;
• and
• a plurality of write select lines,
• wherein, for each of the plurality of memory cells, the access transistor, the control gate transistor, and the resistive element are connected to one another in series, a gate terminal of the access transistor and a gate terminal of the control gate transistor are connected to first and second source/drain terminals of the read select transistor, respectively, and the gate terminal of the control gate transistor and a corresponding one of the control gate lines are connected to first and second source/drain terminals of the write select transistor, respectively.