Memory devices and methods of manufacturing thereof

A memory circuit, comprising:

• a memory array comprising a plurality of memory cells arranged over a plurality of word lines extending along a first lateral direction, a plurality of reference lines extending along a second lateral direction perpendicular to the first lateral direction, and a plurality of signal lines extending along the second lateral direction;
• wherein each of the memory cells is selected from one of a first memory cell, a second memory cell, a third memory cell, or a fourth memory cell;
• wherein the first memory cell having its first and second source/drain terminals both connected to a corresponding one of the plurality of reference lines;
• wherein the second memory cell having its first and second source/drain terminals both connected to a corresponding one of the plurality of signal lines;
• wherein the third memory cell having its first and second source/drain terminals connected to a corresponding one of the plurality of signal lines and a corresponding one of the plurality of reference lines, respectively;
• and
• wherein the fourth memory cell having its first and second source/drain terminals connected to a corresponding one of the plurality of reference lines and a corresponding one of the plurality of signal lines, respectively.

A method for programming a memory circuit, comprising:

• forming an initial one of a plurality of memory cell as one of first, second, third, or fourth memory cell, wherein the first memory cell has its first and second source/drain terminals both connected to a reference line, the second memory cell has its first and second source/drain terminals both connected to a signal line, the third memory cell has its first and second source/drain terminals connected to the signal line and the reference line, respectively, the fourth memory cell has its first and second source/drain terminals connected to the reference line and the signal line, respectively;
• based on the initial memory cell being formed as the first memory cell, forming an immediately next one of the plurality of memory cells as the first or third memory cell;
• based on the initial memory cell being formed as the second memory cell, forming the immediately next memory cell as the second or fourth memory cell;
• based on the initial memory cell being formed as the third memory cell, forming the immediately next memory cell as the second or fourth memory cell;
• and
• based on the initial memory cell being formed as the fourth memory cell, forming the immediately next memory cell as the first or third memory cell.