Memory device, method of operating thereof, and memory system

A memory device, comprising:

• a memory cell array comprising a plurality of memory cells, wherein each of the memory cells is in one of Q×2K states, wherein states of two memory cells coupled to a same word line form a plurality of state combinations for storing Q+2K bits of data, and Q and K are both integers;
• and
• a peripheral circuit coupled to the memory cell array, wherein when reading each bit in Q bits of data, the peripheral circuit is configured to:
• applying a first read voltage to a selected word line;
• and
• after applying the first read voltage, applying a second read voltage to the selected word line.

A method of operating a memory device, comprising:

• applying a first read voltage to a selected word line when reading each bit in Q bits of data;
• and
• after applying the first read voltage, applying a second read voltage to the selected word line;
• wherein the memory device comprises a memory cell array comprising a plurality of memory cells, each of the memory cells is in one of Q×2K states, states of two memory cells coupled to a same word line form a plurality of state combinations for storing Q+2K bits of data, and Q and K are both integers.