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US 2026/0237431 A1Published application
In-memory acceleration using 6t-rrams with signed weight values
AssigneeGovernment of the United States as Represented by the Secretary of the Air Force
InventorsKang Jun Bai, Hao Jiang
Life of this patent
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Abstract
A memristive circuit includes a signal source; a bit line; and a six-transistor, one-resistive random-access memory (6T1R) cell. The RRAM element is configured to store a plurality of resistance states corresponding to magnitudes of synaptic weights, a sign and magnitude of the synaptic weight being determined by a direction and a magnitude of current conducted through the RRAM element via one of the positive-weight conduction loop and the negative-weight conduction loop; and during a read operation, the resistance state of the RRAM element modulates a current on the bit line, a magnitude of the current thereby representing the magnitude of the synaptic weight.
Claims15
A memristive circuit comprising:
- a signal source;
- a bit line;
- and
- a six-transistor, one-resistive random-access memory (6T1R) cell comprising:
- a resistive random-access memory (RRAM) element having a first terminal and a second terminal, the second terminal being electrically coupled to the bit line;
- a positive-weight conduction loop comprising:
- a first transistor (M1) having a gate configured to receive a positive-state gate voltage (Vp), a source coupled to the signal source, and a drain configured to control a state of a logic inverter, wherein the first transistor is configured to selectively pass the signal source to the logic inverter;
- the logic inverter, comprising a third transistor (M3) and a fourth transistor (M4), each having gates coupled to the drain of M1, the logic inverter having an output;
- and
- a fifth transistor (M5) having a gate coupled to the output of the logic inverter, a source coupled to a training supply voltage (VDD), and a drain coupled to the first terminal of the RRAM element;
- and
- a negative-weight conduction loop comprising:
- a second transistor (M2) having a source coupled to the signal source and a gate configured to receive a negative-state gate voltage (Vn);
- and
- a sixth transistor (M6) having a gate coupled to a draing of the second transistor, a drain coupled to the first terminal of the RRAM element, and a source coupled to ground;
- and wherein
- the RRAM element is configured to store a plurality of resistance states corresponding to magnitudes of synaptic weights, a sign and magnitude of the synaptic weight being determined by a direction and a magnitude of current conducted through the RRAM element via one of the positive-weight conduction loop and the negative-weight conduction loop;
- and
- during a read operation, the resistance state of the RRAM element modulates a current on the bit line, a magnitude of the current thereby representing the magnitude of the synaptic weight.
16 more elements
An array of memristive circuit cells comprising:
- a word line;
- a bit line;
- a plurality of a six-transistor, one-resistive random-access memory (6T1R) cells coupled between the word line and bit line, each cell comprising:
- a resistive random-access memory (RRAM) element having a first terminal and a second terminal, the second terminal being electrically coupled to the bit line;
- a positive-weight conduction loop comprising:
- a first transistor (M1) having a gate configured to receive a positive-state gate voltage (Vp), a source coupled to the word line, and a drain configured to control a state of a logic inverter, wherein the first transistor is configured to selectively pass the signal source to the logic inverter;
- the logic inverter, comprising a third transistor (M3) and a fourth transistor (M4), each having gates coupled to the drain of M1, the logic inverter having an output;
- and
- a fifth transistor (M5) having a gate coupled to the output of the logic inverter, a source coupled to a training supply voltage (VDD), and a drain coupled to the first terminal of the RRAM element;
- and
- a negative-weight conduction loop comprising:
- a second transistor (M2) having a source coupled to the word line and a gate configured to receive a negative-state gate voltage (Vn);
- and
- a sixth transistor (M6) having a gate coupled to a drain of the second transistor, a drain coupled to the first terminal of the RRAM element, and a source coupled to ground;
- and wherein
- each RRAM element is configured to store a plurality of resistance states corresponding to magnitudes of synaptic weights, a sign and magnitude of the synaptic weight being determined by a direction and a magnitude of current conducted through the RRAM element via one of the positive-weight conduction loop and the negative-weight conduction loop,
- asserting a voltage on the word line selects each cell coupled thereto by providing an input voltage to the source of the first transistor (M1) and the source of the second transistor (M2), thereby enabling one of the positive-weight conduction loop and the negative-weight conduction loop to modify the resistance state of the RRAM element, and
- during a read operation, the resistance state of the RRAM element modulates a current on the bit line, a magnitude of the current thereby representing the magnitude of the synaptic weight.
15 more elements
Dependencies are inferred from the claim text.