Memory device
AssigneeKioxia Corporation
InventorsAkira KATAYAMA, Kosuke HATSUDA
Life of this patent
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Abstract
A first memory cell includes a first variable resistance element and a first switching element coupled to the first variable resistance element. A first interconnect is coupled to the first memory cell. A first switch has a first end and a second end, the first end being coupled to the first interconnect. A second interconnect is coupled to the second end. A first pre-charge circuit is coupled to the second interconnect. A first transistor has a third end, a fourth end, and a gate, the third end being coupled to a first node receiving a first voltage, the gate being coupled to the first interconnect. A third interconnect is coupled to the fourth end of the first transistor. A sense amplifier circuit is coupled to the third interconnect.
Claims17
A memory device comprising:
- a first memory cell that includes a first variable resistance element and a first switching element coupled to the first variable resistance element;
- a first interconnect coupled to the first memory cell;
- a first switch that has a first end and a second end, the first end being coupled to the first interconnect;
- a second interconnect coupled to the second end;
- and
- a first pre-charge circuit coupled to the second interconnect;
- a first transistor that has a third end, a fourth end, and a gate, the third end being coupled to a first node receiving a first voltage, the gate being coupled to the first interconnect;
- a third interconnect coupled to the fourth end of the first transistor;
- and
- a sense amplifier circuit coupled to the third interconnect.
Dependencies are inferred from the claim text.