Shift register, gate driving circuit, and driving method for shift register

A shift register comprising:

• a cascade output sub-circuit, an output control sub-circuit, and a scan output sub-circuit;
• the cascade output sub-circuit is electrically connected to an input terminal, a first clock signal terminal, a second clock signal terminal, a first power supply terminal, a second power supply terminal, a cascade output terminal, a first node, a second node, and a third node respectively, and is configured to provide a signal of the first power supply terminal or the second power supply terminal to the cascade output terminal under control of signals of the input terminal, the first clock signal terminal, the second clock signal terminal, the first node, the second node, and the third node;
• the output control sub-circuit is electrically connected to a first control signal terminal, a second control signal terminal and a third control signal terminal, the first node, the second node, the third node, a fourth node, and a fifth node respectively, and is configured to provide a signal of the first node to the fourth node and to provide a signal of the second node to the fifth node under control of signals of the first node, the third node, and the first control signal terminal to the third control signal terminal;
• and
• the scan output sub-circuit is electrically connected to the fourth node, the fifth node, a scan signal output terminal, the first power supply terminal, and the second power supply terminal, respectively, and is configured to output the signal of the first power supply terminal or the second power supply terminal to the scan signal output terminal under control of signals of the fourth node and the fifth node.