Learning device, inference device, and semiconductor device

A semiconductor device, comprising:

• a plurality of bus masters;
• a plurality of bus slaves;
• a bus, interconnecting the plurality of bus masters and the plurality of bus slaves, for address transfers and data transfers between the plurality of bus masters and the plurality of bus slaves;
• and
• a bus control device to control the address transfers and the data transfers via the bus, the bus control device including:
• a memory device storing past transfer requests output from plurality of bus masters, priorities set to the transfer requests, and bus occupancy times by the data transfers based on the transfer requests;
• and
• a learning device, including:
• a data obtainer which obtains, as training data, an attribute of a transfer request whose bus occupancy time is shorter than a first occupancy time among the past transfer requests and a priority of the transfer request from the memory device;
• and
• a model generator which generates, using the training data, a learned model for estimating, from the attribute of the transfer request, a priority allowing the bus occupancy time to be shorter than the first occupancy time.

A learning device, comprising:

• a data obtainer to obtain training data including conflicting transfer requests from a plurality of bus masters and a transfer request to be granted a bus access right among the conflicting transfer requests from the plurality of bus masters;
• and
• a model generator to generate, using the training data, a learned model for determining, from conflicting transfer requests from a plurality of bus masters, the transfer request to be granted the bus access right among the conflicting transfer requests from the plurality of bus masters wherein
• when an average transaction time decreases due to the bus access right being granted, the model generator increases a reward, and when the average transaction time increases due to the bus access right being granted, the model generator reduces a reward.