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AssigneeMicrosoft Technology Licensing, LLC
InventorsPing LU, Bupesh PANDITA, Minhan CHEN
Estimating the term…
In a calibrated phase-locked loop (PLL), a time-to-digital (TDC) converter circuit can be calibrated to a nominal gain by a calibration circuit to achieve a desired jitter response in the PLL. The TDC circuit in the PLL measures a time difference between the reference clock and a feedback signal as a number of time increments, and the calibration circuit adjusts a resolution of the measurement by adjusting the length of the time increments (i.e., resolution). In a Vernier method employed to measure the time difference, the length of a time increment is determined by a delay difference between a first delay of a first delay circuit in a first series of first delay circuits and a second delay of a second delay circuit in a second series of second delay circuits. Adjusting the resolution of the TDC circuit includes adjusting the delay difference between the first delay and the second delay.
A processor-based device, comprising:
The processor-based device of any one of claims 1-2, wherein the processor is further configured to clear the BSE indicator subsequent to execution of the instruction stored in the BSR 4. The processor-based device of any one of claims 1-3, wherein the processor is further configured to continue execution of the software process at a next instruction following the software breakpoint instruction in the system memory, subsequent to execution of the instruction stored in the BSR 5. The processor-based device of any one of claims 1-4, wherein:
The processor-based device of claim 5, wherein the processor is further configured to execute the exception handler to:
A method for efficiently replacing software breakpoint instructions, comprising:
A computer-readable medium having stored thereon an instruction program comprising a plurality of computer-executable instructions for execution by a processor of a processor-based device which, when executed by the processor, causes the processor to:
The computer-readable medium of any one of claims 17-18, wherein the plurality of computer-executable instructions further cause the processor to clear the BSE indicator subsequent to execution of the instruction stored in the BSR 20. The computer-readable medium of any one of claims 17-19, wherein the plurality of computer-executable instructions further cause the processor to continue execution of the software process at a next instruction following the software breakpoint instruction in the system memory, subsequent to execution of the instruction stored in the BSR
Dependencies are inferred from the claim text.