Memory system, controller, and method of controlling memory

A controller comprising:

• a processor;
• and
• a memory interface configured to connect the processor and a memory in which data having been encoded with an error-correcting code for correcting an error of t bits or less (t is an integer of 2 or more) is stored, wherein
• the processor is configured to
• read a received word from the memory via the memory interface,
• calculate at least t syndromes by using the read received word,
• calculate, by executing variable transformation on the calculated syndrome, (t−1) pieces of key information for determining one or more first error patterns each including a combination of post-transformation positions, the post-transformation positions being acquired by applying the variable transformation to error positions in a case of the number of error bits being (t+1),
• determine the one or more first error patterns corresponding to the calculated key information by using correspondence information in which possible values for the key information and the one or more first error patterns are correlated with each other,
• calculate the error positions by executing variable inverse transformation on the post-transformation positions included in each of the one or more first error patterns,
• determine a list including one or more second error patterns, the second error patterns each including a combination of the calculated error positions, and
• execute list decoding by using the list.

A computer-implemented method of controlling a memory, the method comprising:

• storing, in the memory, data having been encoded with an error-correcting code for correcting an error of t bits or less (t is an integer of 2 or more);
• reading a received word from the memory;
• calculating at least t syndromes by using the read received word;
• calculating, by executing variable transformation on the calculated syndrome, (t−1) pieces of key information for determining one or more first error patterns each including a combination of post-transformation positions, the post-transformation positions being acquired by applying the variable transformation to error positions in a case of the number of error bits being (t+1);
• determining the one or more first error patterns corresponding to the calculated key information by using correspondence information in which possible values for the key information and the one or more first error patterns are correlated with each other;
• calculating the error positions by executing variable inverse transformation on the post-transformation positions included in each of the one or more first error patterns;
• determining a list including one or more second error patterns, the second error patterns each including a combination of the calculated error positions;
• and
• executing list decoding by using the list.