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US 2026/0236266 A1Published application
Shadow cache for securing conditional speculative instruction execution
AssigneeLodestar Licensing Group LLC
InventorSteven Jeffrey Wallach
Life of this patent
Estimating the term…
Abstract
A computing device, having: a processor; memory; a first cache coupled between the memory and the processor; and a second cache coupled between the memory and the processor. During speculative execution of one or more instructions, effects of the speculative execution are contained within the second cache.
Claims20
A method at a computing device, comprising:
- receiving a branch instruction and an associated set of instructions for speculative execution;
- determining an object identifier of an address for an instruction of the set of instructions;
- and
- determining whether to speculatively execute the set of instructions based at least in part on the object identifier of the address and on a static object identifier associated with a kernel object.
1 more element
A computing device, comprising:
- a processor configured to:
- receive a branch instruction and an associated set of instructions for speculative execution;
- determine an object identifier of an address for an instruction of the set of instructions;
- and
- determine whether to speculatively execute the set of instructions based at least in part on the object identifier of the address and on a static object identifier associated with a kernel object.
2 more elements
A system, comprising:
- a memory;
- and
- a processor coupled with the memory and configured to:
- receive a branch instruction and an associated set of instructions for speculative execution;
- determine an object identifier of an address for an instruction of the set of instructions;
- and
- determine whether to speculatively execute the set of instructions based at least in part on the object identifier of the address and on a static object identifier associated with a kernel object.
4 more elements
Dependencies are inferred from the claim text.