Contention avoidance delays for accesses to shared memory locations

Abstract

Apparatuses, systems, chip-containing products, non-transitory computer-readable media and methods are disclosed. Load/store circuitry initiates a memory system transaction to access a shared memory location, wherein the shared memory location is accessible to multiple concurrent program threads. In response to an indication of concurrent access to the shared memory location by another program thread, the load/store circuitry causes a delay of reissuance of the memory system transaction by a delay period, wherein delay circuitry is configured to set the delay period in dependence on at least one factor determined at runtime.

Dependencies are inferred from the claim text.