Refresh command for multiple memory banks of multiple memory dies
AssigneesAdvanced Micro Devices, Inc., ATI Technologies ULC
InventorsMichael LITT, Yubin YAO
Life of this patent
Estimating the term…
Abstract
A memory system includes one or more memory dies and a memory controller. The one or more memory dies have a first memory bank, a second memory bank, a third memory bank, and a fourth memory bank. The first memory bank is associated with a first identifier and the third memory bank is associated with a second identifier. The memory controller circuitry is coupled to the one or more memory dies. The memory controller circuitry outputs a refresh command to the one or more memory dies to refresh the first memory bank and the third memory bank during a first period. The second memory bank and the fourth memory bank are accessible by the memory controller circuitry during the first period.
Claims20
A memory system comprising:
- one or more memory dies having a first memory bank, a second memory bank, a third memory bank, and a fourth memory bank, wherein the first memory bank is associated with a first identifier and the third memory bank is associated with a second identifier;
- and
- memory controller circuitry coupled to the one or more memory dies, wherein the memory controller circuitry is configured to output a refresh command to the one or more memory dies to refresh the first memory bank and the third memory bank during a first period, and wherein the second memory bank and the fourth memory bank are accessible by the memory controller circuitry during the first period.
A memory controller of a memory system configured to:
- output a refresh command to one or more memory dies of the memory system to refresh a first memory bank of the one or more memory dies and a third memory bank of the one or more memory dies during a first period, and wherein a second memory bank of the one or more memory dies and a fourth memory bank of the one or more memory dies are accessible by the memory controller during the first period.
A method comprising:
- outputting, from memory controller circuitry to one or more memory dies, a refresh command;
- and
- refreshing, a first memory bank of the one or more memory dies and a third memory bank of the one or more memory dies during a first period based on the refresh command, wherein a second memory bank of the one or more memory dies and a fourth memory bank of the one or more memory dies are accessible by the memory controller circuitry during the first period.
Dependencies are inferred from the claim text.