Functional verification

Abstract

A method for functional verification of a circuit design under test (DUT), comprises: generating stimulus inputs for first and second DUT instances instantiated for testing using a functional verification test bench, where the first and second DUT instances are each based on a same functional design for the circuit DUT comprising at least one clock gate configured to control, based on a clock gating control input, whether a clock signal is enabled or disabled for downstream circuitry, and the stimulus inputs comprise at least one clock gating control input being set differently for the first and second DUT instances and non-clock-gating control inputs set identically for the first and second DUT instances; using the functional verification test bench, stimulating a response of the first and second DUT instances to the stimulus inputs, to obtain test outputs for the first and second DUT instances; and using at least one output checker, comparing at least one pair of corresponding test outputs for the first and second DUT instances, to detect whether there is divergence between behaviour of the first and second DUT instances.

Dependencies are inferred from the claim text.