Jitter measurement circuit and method of measuring jitter performed by the same

A method of measuring a jitter, comprising:

• outputting, based on a first clock signal, a second clock signal, the second clock signal being delayed from the first clock signal;
• delaying, by a plurality of first delay cells, the first clock signal based on a control signal;
• delaying, by a plurality of second delay cells, the second clock signal;
• determining, as a first resolution, a resolution of a time-to-digital converter based on a phase difference between a plurality of first delay clock signals and a plurality of second delay clock signals, the plurality of first delay clock signals being generated based on passing the first clock signal through the plurality of first delay cells, the plurality of second delay clock signals being generated based on passing the second clock signal through the plurality of second delay cells, and the resolution of the time-to-digital converter being configured to change depending on a level of the jitter of the first clock signal;
• and
• outputting, based on the first resolution, a result signal corresponding to the level of the jitter.

A jitter measurement circuit comprising:

• a time-to-digital converter including a plurality of first delay cells, a plurality of second delay cells, and a plurality of first phase detectors, the plurality of first delay cells being configured to output a plurality of first delay clock signals by delaying a first clock signal based on a control signal, the plurality of second delay cells being configured to output a plurality of second delay clock signals by delaying a second clock signal, the second clock signal being delayed from the first clock signal, the plurality of first phase detectors being connected between the plurality of first delay cells and the plurality of second delay cells, and the plurality of first phase detectors being configured to output a plurality of first phase detection signals based on a phase difference between the plurality of first delay clock signals and the plurality of second delay clock signals;
• a first delay circuit configured to output the second clock signal based on the first clock signal, the first delay circuit including a second phase detector configured to output a second phase detection signal based on a phase difference between the first clock signal and the second clock signal;
• a resolution circuit configured to
• output the control signal configured to control an amount of delay of the first clock signal,
• determine, based on the plurality of first phase detection signals, a resolution of the time-to-digital converter as a first resolution, and
• output a result signal corresponding to a level of a jitter of the first clock signal, the resolution of the time-to-digital converter being configured to change depending on the level of the jitter;
• a chopper configured to maintain or change a first path of the first clock signal and a second path of the second clock signal based on the first clock signal, the second clock signal, and the second phase detection signal;
• a signal converter configured to output a jitter measurement signal based on the result signal and the second phase detection signal, the jitter measurement signal representing the level of the jitter;
• and
• a resolution estimation circuit configured to estimate, based on two first delay clock signals among the plurality of first delay clock signals, a time corresponding to the first resolution.