Package substrate with a plating layer and a semiconductor package including the same

A semiconductor package comprising:

• a package substrate;
• a semiconductor chip mounted on the package substrate;
• and
• a first connection member and a second connection member connecting the package substrate and the semiconductor chip,
• wherein the package substrate comprises:
• a substrate body, wherein the semiconductor chip is mounted in a chip mounting region of the substrate body;
• a first wiring including a first bonding finger disposed on the substrate body in a bonding finger region of the substrate body, the first bonding finger bonded to the first connection member, the first wiring also including a first trace disposed on the substrate body, the first trace connected to the first bonding finger and extending to the chip mounting region;
• a second wiring including a second bonding finger disposed on the substrate body in the bonding finger region, the second bonding finger bonded to the second connection member, the second wiring also including a second trace disposed on the substrate body, the second trace connected to the second bonding finger and extending to the chip mounting region;
• a first residual section of a first plating inlet line and a second residual section of the first plating inlet line disposed on the substrate body, the first and second residual sections connected to the first and second traces, respectively;
• and
• an insulating layer covering the first trace, the second trace, and the first and second residual sections of the first plating inlet line, the insulating layer having a first opening through which the first bonding finger and the second bonding finger are exposed and a second opening separating the first residual section of the first plating inlet line from the second residual section of the first plating inlet line,
• wherein the first trace includes a recessed section on a side facing the second trace, and the second opening is disposed within the recessed section.