Semiconductor device and methods of formation

A method, comprising:

• forming a recess in a dielectric layer and in an etch stop layer (ESL) of an interconnect layer of a semiconductor device,
• wherein the dielectric layer is above the ESL, and
• wherein the ESL is above a contact structure and a gate structure of an integrated circuit device in a device layer of the semiconductor device;
• depositing, using a first deposition technique, a seed layer on sidewalls and on a bottom surface of the recess;
• performing an oxidation treatment operation for the seed layer,
• wherein the oxidation treatment operation results in formation of oxidized portions of the seed layer on the sidewalls and the bottom surface of the recess, and
• wherein the oxidized portions contain an oxide of a material of the seed layer;
• etching the seed layer to remove the oxidized portions of the seed layer from the sidewalls of the recess,
• wherein an unoxidized portion of the seed layer remains on the bottom surface of the recess;
• and
• depositing, using a second deposition technique that is different than the first deposition technique, material of an interconnect structure on the unoxidized portion of the seed layer that is on the bottom surface of the recess,
• wherein the material of the interconnect structure grows on the unoxidized portion of the seed layer from a bottom of the recess to a top of the recess, and
• wherein the material of the interconnect structure and the material of the seed layer contain different fluorine concentrations.

A semiconductor device, comprising:

• a device layer;
• an integrated circuit device in the device layer;
• and
• an interconnect layer, over the integrated circuit device, comprising:
• a plurality of interlayer dielectric (ILD) layers;
• a plurality of etch stop layers (ESLs) interleaving the plurality of ILD layers;
• a plurality of metallization structures in the plurality of ILD layers;
• and
• a plurality of interconnect structures,
• wherein a first interconnect structure of the plurality of interconnect structures extends vertically through a first ESL of the plurality of ESLs and a first ILD layer of the plurality of ILD layers to couple two or more of the plurality of metallization structures,
• wherein a second interconnect structure extends vertically through a second ESL of the plurality of ESLs and a second ILD layer of the plurality of ILD layers to couple the integrated circuit device to the interconnect layer,
• wherein a first dielectric constant of the second ESL is greater than a second dielectric constant of the second ILD layer, and
• wherein a lateral width of a first portion of the second interconnect structure in the second ESL is greater than a lateral width of a second portion of the second interconnect structure in the second ILD layer.