Cross-couple gate input connections in complementary field-effect transistor cell architecture

A chip, comprising:

• a top gate;
• a first insulator disposed below the top gate;
• a bottom gate;
• a second insulator disposed above the bottom gate;
• a common gate;
• a first source/drain disposed between the top gate and the common gate;
• a second source/drain disposed between the common gate and the second insulator;
• one or more first channels coupled between the first source/drain and the second source/drain, wherein the one or more first channels pass through the common gate;
• a third source/drain disposed between the first insulator and the common gate, wherein the third source/drain is stacked vertically with the first source/drain;
• a fourth source/drain disposed between the common gate and the bottom gate, wherein the fourth source/drain is stacked vertically with the second source/drain;
• and
• one or more second channels coupled between the third source/drain and the fourth source/drain, wherein the one or more second channels pass through the common gate.