Two-rotation gate-edge diode leakage reduction for mos

A metal-oxide-semiconductor (MOS) transistor, comprising:

• a semiconductor substrate surface layer having a well region having a first conductivity type;
• a gate formed over the well region, the gate having a long axis;
• a source/drain region and a source/drain extension to the source/drain region formed in the surface layer, both having a second conductivity type, the source/drain extension extending under the gate;
• a gate edge diode leakage (GDL) reduction region having the second conductivity type extending from under the gate to the source/drain region;
• a first counterdoped pocket portion extending from the GDL-reduction region toward the source/drain region and having the second conductivity type and a lower charge carrier density than the GDL-reduction region;
• and
• a second counterdoped pocket portion extending from the first counterdoped pocket portion to the source/drain region and having the first conductivity type and a lower charge carrier concentration than the well region.

An integrated circuit (IC) comprising:

• a substrate having a surface layer having a top surface;
• first and second metal-oxide-semiconductor (MOS) transistors formed in or over the surface layer, each of the first and second MOS transistors comprising:
• a gate formed over a corresponding well region having a first conductivity type, the gate of the first MOS transistor having a long axis with a first orientation and the gate of the second MOS transistor having a long axis with a second orientation that is about orthogonal to the first orientation in a plane of the top surface;
• a source/drain region and a source/drain extension to the source/drain region formed in the surface layer, both having a second conductivity type, the source/drain extension extending under the gate;
• the first MOS transistor further comprising:
• a pocket region having the first conductivity type extending from under the gate of the first MOS transistor to the source/drain region of the first MOS transistor;
• a first retrograde gate-edge diode leakage (GDL) reduction portion extending from the pocket region toward the source/drain region of the first MOS transistor and having the first conductivity type and a lower charge carrier density than the pocket region;
• and
• a second retrograde GDL-reduction portion extending from the first retrograde GDL-reduction portion to the source/drain region of the first MOS transistor and having the second conductivity type and a lower charge carrier concentration than the source/drain region of the first MOS transistor;
• and
• the second MOS transistor further comprising:
• a GDL-reduction region having the second conductivity type extending from under the gate of the second MOS transistor to the source/drain region of the second MOS transistor;
• a first counterdoped pocket portion extending from the GDL-reduction region toward the source/drain region of the second MOS transistor and having the second conductivity type and a lower charge carrier density than the GDL-reduction region;
• and
• a second counterdoped pocket portion extending from the first counterdoped pocket portion to the source/drain region and having the first conductivity type and a lower charge carrier concentration than the well region of the second MOS transistor.