Three-dimensional flat cell memory device with lateral access transistors and method of making the same

A method of forming a device structure, comprising:

• forming an array of vertical rail stacks, wherein each of the vertical rail stacks comprises, from bottom to top, a first spacer rail, a semiconductor rail, a second spacer rail, and a sacrificial rail, wherein each of the vertical rail stacks laterally extends along a first horizontal direction, and each of the semiconductor rail comprises a respective first semiconductor end wall contacting a respective first capping structure and further comprises a respective second semiconductor end wall contacting a respective second capping structure;
• forming first voids by removing first portions of the sacrificial rails that are proximal to the first capping structures;
• forming first cavities by removing portions of the first spacer rails and the second spacer rails that are proximal to the first voids;
• forming gate dielectrics and gate electrodes in the first cavities to form access transistors;
• forming second voids by removing second portions of the sacrificial rails that are proximal to the second capping structures;
• forming second cavities by removing remaining portions of the first spacer rails and the second spacer rails that are proximal to the second voids;
• and
• forming memory devices that are accessed through the respective access transistors.