3d stacked semiconductor device and manufacturing method therefor, and electronic device

A method for manufacturing a 3D stacked semiconductor device, wherein the 3D stacked semiconductor device comprises a plurality of transistors stacked along a direction perpendicular to a base substrate and distributed in different layers, and the method for manufacturing the 3D stacked semiconductor device comprises:

• providing the base substrate, and sequentially and alternately depositing a first insulation thin film and a first conductive thin film on the base substrate and patterning the first insulation thin film and the first conductive thin film to form a stacked structure, wherein the stacked structure comprises a stack of first insulation layers and conductive layers which are alternately disposed, and a conductive layer of the conductive layers comprises a first conductive portion;
• forming a first sacrificial layer, a second sacrificial layer, and a word line region groove, wherein the word line region groove exposes part of a region other than an end portion of each first conductive portion, and the first sacrificial layer and the second sacrificial layer constitute sidewalls of the word line region groove;
• performing insulation treatment on a conductive layer located in the word line region groove to form an insulation portion, wherein the first conductive portion is partitioned by the insulation portion to form a first sub-portion and a second sub-portion which are independent;
• etching the first sacrificial layer and the second sacrificial layer toward a direction away from the insulation portion to expose the conductive layer connected with the insulation portion, an etched thickness of the first sacrificial layer is smaller than a thickness of the first sacrificial layer along an etched direction, and an etched thickness of the second sacrificial layer is smaller than a thickness of the second sacrificial layer along the etched direction;
• sequentially depositing a semiconductor thin film, a gate insulation thin film, and a gate electrode thin film on the base substrate to form a semiconductor layer, a gate insulation layer and a gate electrode of a transistor of the plurality of transistors respectively, wherein the semiconductor layer surrounds the first sub-portion, the second sub-portion, and the insulation portion, and the gate electrode surrounds a sidewall of the semiconductor layer;
• and
• performing a resistance reduction treatment on the first sub-portion and the second sub-portion to form a first electrode and a second electrode of the transistor respectively.