Dual digital-to-analog converter switching control circuit

A method for generating an analog output signal based on a digital input signal, the method comprising:

• receiving, at a dual digital-to-analog converter, the digital input signal,
• wherein the dual digital-to-analog converter comprises a first digital-to-analog converter and a second digital-to-analog converter;
• receiving, at the dual digital-to-analog converter, a clock signal comprising a high phase and a low phase;
• enabling the first digital-to-analog converter to generate a first analog output portion of the analog output signal based on the digital input signal during the high phase of the clock signal;
• enabling the second digital-to-analog converter to generate a second analog output portion of the analog output signal based on the digital input signal during the low phase of the clock signal;
• closing, by a DAC switching control circuit, a first switch associated with the first digital-to-analog converter during a first DAC settling portion of the low phase of the clock signal;
• and
• opening, by the DAC switching control circuit, the first switch associated with the first digital-to-analog converter during a first DAC open portion of the low phase of the clock signal.

A continuous time sigma-delta analog-to-digital converter, comprising:

• difference amplifier circuitry configured to receive an analog input signal and a feedback analog signal, and generate an analog difference signal between the analog input signal and the feedback analog signal;
• a continuous time loop filter configured to receive the analog difference signal and generate a filtered analog difference signal;
• quantization circuitry configured to receive the filtered analog difference signal and generate a digital output based on a comparison of the filtered analog difference signal to a reference voltage;
• and
• a dual digital-to-analog converter configured to generate the feedback analog signal based on the digital output, the dual digital-to-analog converter comprising:
• a clock signal comprising a high phase and a low phase;
• a first digital-to-analog converter, comprising:
• a first switch, wherein the first digital-to-analog converter is configured to generate a first analog output portion of the feedback analog signal based on the digital output during the high phase of the clock signal;
• a second digital-to-analog converter comprising:
• a second switch, wherein the second digital-to-analog converter is configured to generate a second analog output portion of the feedback analog signal based on the digital output during the low phase of the clock signal;
• and
• a DAC switching control circuit configured to close the first switch during a first DAC settling portion of the low phase of the clock signal and open the first switch during a first DAC open portion of the low phase of the clock signal.