Edge-triggered transceiver in semiconductor package and calibration method thereof

An edge-triggered transceiver, comprising:

• a transmission line disposed in an interposer of a semiconductor package;
• a capacitor coupled to a first end of the transmission line;
• a transmitter configured to receive an input signal and provide a first signal to the capacitor;
• and
• a receiver configured to receive a second signal corresponding to the first signal from the transmission line and provide an output signal, and comprising:
• a first inverter having an input terminal coupled to a second end of the transmission line and an output terminal;
• a first resistor coupled to the input terminal of the first inverter;
• a first switch coupled between the first resistor and a node of a first reference voltage;
• a second switch coupled between the first resistor and a node of a second reference voltage that is less than the first reference voltage;
• a second resistor coupled to the input terminal;
• a third switch coupled between the second resistor and a node of a third reference voltage;
• and
• a fourth switch coupled between the second resistor and a node of a fourth reference voltage that is greater than the third reference voltage,
• wherein the first inverter is configured to receive the second signal and provide a third signal to turn on one of the first switch and the second switch and one of the third switch and the fourth switch.

A calibration method for an edge-triggered transceiver in a semiconductor package, wherein the edge-triggered transceiver comprises a transfer lane disposed in an interposer of the semiconductor package, the calibration method comprising:

• providing a clock signal to a transmitter of the edge-triggered transceiver, so as to provide a first signal to a capacitor of the edge-triggered transceiver, wherein the transfer lane has a first end coupled to the capacitor and a second end coupled to a receiver of the edge-triggered transceiver, wherein the receiver comprises:
• a first inverter having an input terminal coupled to the second end of the transfer lane and an output terminal;
• a first resistor coupled to the input terminal of the first inverter;
• a second resistor coupled between the input terminal and the output terminal of the first inverter;
• a first switch coupled between the first resistor and a node of a first reference voltage;
• and
• a second switch coupled between the first resistor and a node of a second reference voltage that is less than the first reference voltage,
• wherein the first inverter is configured to receive a second signal from the transfer lane and provide a third signal to turn on one of the first switch and the second switch;
• receiving an output signal corresponding to the third signal from the receiver;
• and
• adjusting transitions of the third signal through the first inverter with a control setting, so as to adjust a duty cycle of the output signal to a specific value.