Leakage reduction and biasing circuits
AssigneeGoogle Inc.
InventorsTong Zhang, Andrew Abo, Johan Peter Vanderhaegen
Life of this patent
Estimating the term…
Abstract
A logic circuit (900) includes a power source (Vdd), a biasing circuit (910), a digital cell (904), a first p-channel metal oxide semiconductor (PMOS) (902) electrically connected between the power source and the digital cell, a second PMOS (906) electrically connected between the power source and a first input (908, INP) of the biasing circuit, and a third PMOS (912) electrically connected between the power source and a second input (914, INM) of the biasing circuit, wherein the digital cell is connected to a common mode voltage (908, virtual Vdd) of the biasing circuit, such that the common mode voltage of the biasing circuit is substantially equal to a voltage (virtual Vdd) received by the digital cell.
Claims24
A logic circuit comprising:
- a power source;
- a biasing circuit;
- a digital cell;
- a first p-channel metal oxide semiconductor (PMOS) electrically connected between the power source and the digital cell;
- a second PMOS electrically connected between the power source and a first input of the biasing circuit;
- and
- a third PMOS electrically connected between the power source and a second input of the biasing circuit;
- wherein the digital cell is connected to a common mode voltage of the biasing circuit, such that the common mode voltage of the biasing circuit is substantially equal to a voltage received by the digital cell.
A logic circuit comprising:
- a power source;
- a digital cell;
- and
- a biasing circuit comprising:
- a first p-channel metal oxide semiconductor (PMOS) electrically connected between the power source and the digital cell;
- a second PMOS electrically connected between the power source and a first input of the biasing circuit;
- and
- a third PMOS electrically connected between the power source and a second input of the biasing circuit;
- wherein the digital cell is connected to a common mode voltage of the biasing circuit, such that the common mode voltage of the biasing circuit is substantially equal to a voltage received by the digital cell.
A method performed by a logic circuit comprising:
- a power source,
- a biasing circuit,
- a digital cell,
- a first p-channel metal oxide semiconductor (PMOS) electrically connected between the power source and the digital cell,
- a second PMOS electrically connected between the power source and a first input of the biasing circuit, and
- a third PMOS electrically connected between the power source and a second input of the biasing circuit, wherein the digital cell is connected to a common mode voltage of the biasing circuit,
- the method comprising generating, by the logic circuit, a common mode voltage of the biasing circuit that is substantially equal to a voltage received by the digital cell.
A method performed by a logic circuit comprising:
- a power source,
- a digital cell, and
- a biasing circuit comprising:
- a first p-channel metal oxide semiconductor (PMOS) electrically connected between the power source and the digital cell;
- a second PMOS electrically connected between the power source and a first input of the biasing circuit;
- and
- a third PMOS electrically connected between the power source and a second input of the biasing circuit;
- wherein the digital cell is connected to a common mode voltage of the biasing circuit,
- the method comprising generating, by the logic circuit, a common mode voltage of the biasing circuit that is substantially equal to a voltage received by the digital cell.
Dependencies are inferred from the claim text.