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US 2026/0230067 A1Published application
All-digital transient filter for serial communication links
AssigneeSTMicroelectronics International N.V.
InventorsAnkur BAL, Aradhana KUMARI
Life of this patent
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Abstract
In accordance with various embodiments of the present disclosure, a transient filter circuit is provided. In some embodiments, the transient filter circuit comprises a rising edge flip-flop (RE FF) and a falling edge flip-flop (FE FF) in parallel to the RE FF. An output signal from the RE FF prevents the FE FF from being triggered by falling edge transients in an input signal to be filtered. An output signal from the FE FF prevents the RE FF from being triggered by rising edge transients in the input signal.
Claims17
A transient filter circuit comprising:
- a rising edge flip-flop (RE FF);
- and
- a falling edge flip-flop (FE FF) in parallel to the RE FF;
- wherein an output signal from the RE FF prevents the FE FF from being triggered by falling edge transients in an input signal to be filtered;
- and
- wherein an output signal from the FE FF prevents the RE FF from being triggered by rising edge transients in the input signal.
3 more elements
An electronic device comprising:
- (i) a transient filter circuit comprising:
- a rising edge flip-flop (RE FF);
- and
- a falling edge flip-flop (FE FF) in parallel to the RE FF;
- wherein an output signal from the RE FF prevents the FE FF from being triggered by falling edge transients in an input signal to be filtered;
- and
- wherein an output signal from the FE FF prevents the RE FF from being triggered by rising edge transients in the input signal;
- and
- (ii) receiving circuitry connected to an output of the transient filter circuit to receive a filterer version of the input signal.
6 more elements
A transient filter circuit comprising:
- a rising edge flip-flop (RE FF);
- a falling edge flip-flop (FE FF) in parallel to the RE FF;
- an upstream AND gate having a first input that receives an input signal, a second input that receives an output signal from the FE FF, and an output that is connected to a clock input of the RE FF;
- an upstream OR gate having a first input that receives the input signal, a second input that receives an output signal from the RE FF, and an output that is connected to a clock input of the FE FF;
- first delay circuitry having an input connected to an output of the RE FF and an output connected to a reset input of the RE FF, the first delay circuitry creating a first time delay defining an amount of time after the input signal transitions from low to high for which any transients in the input signal will be filtered;
- second delay circuitry having an input connected to an output of the FE FF and an output connected to a set input of the FE FF, the second delay circuitry creating a second time delay defining an amount of time after the input signal transitions from high to low for which any transients in the input signal will be filtered;
- a first downstream AND gate having a first input connected to an inverse output of the RE FF, a second input connected to an inverse output of the FE FF, and an output connected to a first input of a latch;
- and
- a second downstream AND gate having a second input connected to an output of the RE FF, a second input connected to an output of the FE FF, and an output connected to a second input of the latch;
- wherein an output signal from the RE FF prevents the FE FF from being triggered by falling edge transients in an input signal to be filtered;
- wherein an output signal from the FE FF prevents the RE FF from being triggered by rising edge transients in the input signal;
- wherein the latch latches and outputs a high signal when the input signal transitions from low to high and latches and outputs a zero when the input signal transitions from high to low.
9 more elements
Dependencies are inferred from the claim text.