Clock latch with integrated test signal

A clock latch system, comprising:

• a front-end circuit comprising a logic gate with multiple input terminals;
• a latch circuit connected to the front-end circuit, the latch circuit comprising:
• a transmission gate configured to receive an enable output from the front-end circuit;
• a state node connected to the transmission gate;
• and
• a plurality of transistors connected to the state node and controlled by at least one test signal;
• an output driver circuit connected to the state node;
• and
• a clock generation circuit connected to the latch circuit, the clock generation circuit configured to control clock gating based on the at least one test signal.

A clock latch system, comprising:

• a front-end circuit comprising a logic gate having multiple input terminals and configured to produce an enable output;
• a latch circuit connected to the front-end circuit, the latch circuit comprising:
• a transmission gate configured to receive the enable output;
• a state node connected to the transmission gate;
• an inverting buffer connected to the state node;
• and
• a feedback tri-state buffer connected between an output of the inverting buffer and the state node;
• an output circuit connected to the state node, the output circuit comprising a test signal transistor having a gate connected to a scan shift enable (SSE) signal;
• and
• a clock generation circuit connected to the latch circuit, the clock generation circuit comprising power reduction functionality configured to gate a clock signal based on consecutive unchanged values of the enable output.