Input/output circuit for memory and operating method thereof

An input/output circuit for a memory array having a first bit line and a second bit line, comprising:

• a bypass circuit configured to directly receive a data signal and indirectly receive a write enable signal to generate a first signal;
• a first latch circuit coupled between a first data line and a second data line, and comprising:
• a first inverter having an input for receiving the first signal;
• a first switch coupled between the first data line and the input of the first inverter;
• and
• a second switch coupled between the second data line and an output of the first inverter;
• a second latch circuit coupled to the first latch circuit and configured to generate a data output signal based on a voltage of the second data line;
• a first transistor coupled to the first latch circuit and gated by a sense enable signal;
• a second transistor coupled to the first latch circuit and gated by a clock signal;
• a third transistor coupled between the first bit line and the first data line;
• and
• a fourth transistor coupled between the second bit line and the second data line,
• wherein the first transistor and the second transistor are alternately activated in each of a plurality of operation modes comprising a read mode, a write mode and a test mode,
• wherein the first inverter and the bypass circuit are configured to be powered by a first power supply voltage, and the memory array, the first latch circuit except the first inverter, and the second latch circuit are configured to be powered by a second power supply voltage different from the first power supply voltage.

A method for operating an input/output circuit of a memory array, comprising:

• directly receiving a data signal and indirectly receiving a write enable signal to generate a bypass data signal, by a bypass circuit;
• transmitting the bypass data signal to a first latch, wherein the first latch is coupled to the memory array through a first data line and a second data line, and the first latch comprises:
• a first inverter having an input for receiving the bypass data signal;
• a first switch coupled between the first data line and the input of the first inverter;
• and
• a second switch coupled between the second data line and an output of the first inverter;
• transmitting a logic inverse of the bypass data signal to the first latch;
• generating a data output signal based on a voltage presented on the second data line, by a second latch;
• providing a first power supply voltage to power the first inverter and the bypass circuit;
• and
• providing a second power supply voltage to power the memory array, the first latch except the first inverter, and the second latch, wherein the second power supply voltage is different from the first power supply voltage.