Super cell design for ground core memory cell structure to narrow down icell distribution in non-volatile memory

A method, comprising:

• receiving a plurality numerical weight values for a neural network;
• converting the weight values to corresponding current states;
• programming the current states into memory cells of a three dimensional NAND memory structure in order to program the weight values into the memory cells, the three dimensional NAND memory structure having alternating conducting layers and insulating layers with NAND strings extending perpendicularly through the alternating conducting layers and insulating layers, each NAND string having a plurality of NAND memory cells and a conductive core, the alternating conductive layers comprising multiple word line layers between one or more first select layers and one or more second select gate layers, and the select gate layers of the first set and the second set forming transistors that have a channel layer region of a first length, a first plurality of contiguous word line layers that form transistors that have a channel layer region of a second length longer than the first length, and the memory cells of the first plurality of contiguous word lines storing weights of a neural network;
• receiving an input vector of a plurality of values for the neural network;
• converting each of the plurality of values of the input vector to corresponding voltage levels;
• and
• performing an in-memory compute operation to multiply the input vector with the weight values, including:
• applying input vector to the three dimensional NAND memory structure as the corresponding voltage levels while concurrently biasing the conductive core to ground.

A computational device, comprising:

• a three dimensional NAND memory structure having alternating conducting layers and insulating layers, the three dimensional NAND memory structure having NAND strings extending perpendicularly through the alternating conducting layers and insulating layers, each NAND string having a plurality of NAND memory cells and a conductive core, the alternating conductive layers comprising multiple word line layers between one or more first select layers and one or more second select gate layers, and the select gate layers of the first set and the second set forming transistors that have a channel layer region of a first length, a first plurality of contiguous word line layers that form transistors that have a channel layer region of a second length longer than the first length, and the memory cells of the first plurality of contiguous word lines storing weights of a neural network;
• and
• one or more control circuits in communication with the three dimensional NAND memory structure and configured to:
• receive an input vector of a plurality of values;
• convert each of the plurality of values of the input vector to a corresponding voltage level;
• and
• perform an in-memory compute operation to multiply the input vector with the weighs of the neural network, including applying input vector to the three dimensional NAND memory structure as the corresponding voltage levels while concurrently biasing the conductive core to ground.