US 2026/0229300 A1 · MULTI-PASS PROGRAMMING TECHNIQUES FOR MEMORY DEVICES

Abstract

The memory device includes memory blocks with arrays of memory cells that are arranged in word lines. Circuitry is configured to program four pages of user data into the memory cells of a selected word line of a selected memory block in a multi-pass programming operation. In a first programming pass, the circuitry programs foggy data into the memory cells of the selected word line. In at least one parity memory block, the circuitry programs two pages of parity data. Prior to a second programming pass, the circuitry reads the foggy data to retrieve two pages of user data and reads the parity data to retrieve the other two pages of user data. The circuitry then combines the pages from the foggy data and the pages from the selected word line to recreate the four pages of user data.

Claims20

Dependent claims

A method of programming a memory device, comprising the steps of:

preparing a plurality of memory blocks, each of the memory blocks including an array of memory cells that are arranged in a plurality of word lines;
in a selected memory block of the plurality of memory blocks, in a first programming pass, programming foggy data into the memory cells of a selected word line of the plurality of word lines;
in at least one parity memory block of the plurality of memory blocks, programming two pages of parity data;
reading the foggy data to retrieve two pages pages of user data;
reading the parity data to retrieve two other pages of user data;
and
combining the two pages of user data from the foggy data and the two other pages of user data to recreate four pages of user data.

4 more elements

Dependencies are inferred from the claim text.

Multi-pass programming techniques for memory devices

Life of this patent

Multi-pass programming techniques for memory devices

Life of this patent

Abstract

Claims20