Word line bit ignore parameters in a memory device

A memory device, comprising:

• a memory block that includes an array of memory cells that are arranged in a plurality of word lines;
• circuitry that is configured to program the memory cells of a selected word line of the plurality of word lines, the circuitry being configured to;
• determine if a selected word line of the plurality of word lines is in a first zone of the memory block,
• in response to the selected word line being in the first zone of the memory block, set a bit scan pass fail (BSPF) criteria at a first level,
• in response to the selected word line not being in the first zone of the memory block, set the BSPF criteria at a second level that is different than the first level, and
• program the memory cells of the selected word line in a plurality of program loops that include bitscan operations that utilize the BSPF criteria.

An apparatus, comprising:

• a memory block that includes an array of memory cells that are arranged in a plurality of word lines;
• a programming means that for programming the memory cells of a selected word line of the plurality of word lines, the programming means being configured to;
• determine if a selected word line of the plurality of word lines is in a first zone of the memory block,
• in response to the selected word line being in the first zone of the memory block, set a bit scan pass fail (BSPF) criteria at a first level,
• in response to the selected word line not being in the first zone of the memory block, set the BSPF criteria at a second level that is different than the first level, and
• program the memory cells of the selected word line in a plurality of program loops that include bitscan operations that utilize the BSPF criteria.