Semiconductor device and memory system

A memory system, comprising:

• a plurality of semiconductor devices each including:
• a first voltage line to which a first voltage is supplied;
• a second voltage line to which a second voltage lower than the first voltage and a first current corresponding to the second voltage are supplied;
• a third voltage line to which a third voltage and a second current corresponding to the third voltage are supplied;
• a fourth voltage line to which a fourth voltage higher than the second voltage and lower than the first voltage is supplied;
• a reference voltage line to which a reference voltage that is lower than the second voltage and that serves as a reference is supplied;
• a first voltage generation circuit electrically connected to the first voltage line, the third voltage line, and the reference voltage line, and configured to generate the third voltage and the second current;
• a second voltage generation circuit electrically connected to the first voltage line, the fourth voltage line, and the reference voltage line, and configured to generate the fourth voltage;
• a memory unit electrically connected to the first voltage line and the reference voltage line;
• an interface circuit electrically connected to the second voltage line, the third voltage line, and the reference voltage line;
• and
• an internal circuit electrically connected to the fourth voltage line, the reference voltage line, the interface circuit, and the memory unit;
• and
• a control circuit including a memory device storing a plurality of set values and a plurality of programs, and configured to adjust a ratio between the first current supplied to the second voltage line and the second current supplied to the third voltage line, wherein
• the memory unit of each of the plurality of semiconductor devices includes a memory cell array including a plurality of blocks, and
• the plurality of set values include a first set value for setting activation or deactivation of the first voltage generation circuit, a plurality of second set values for setting the ratio, a third set value for setting at least one semiconductor device to be used among the plurality of semiconductor devices, and a fourth set value for setting at least one block to be used in the memory unit of the at least one semiconductor device to be used.

A memory system, comprising:

• a first voltage line to which a first voltage is supplied;
• a second voltage line to which a second voltage lower than the first voltage is supplied;
• a third voltage line to which a third voltage same as the second voltage is supplied;
• a fourth voltage line to which a fourth voltage lower than the third voltage is supplied;
• a reference voltage line to which a reference voltage that is lower than the fourth voltage and that serves as a reference is supplied;
• a control circuit including:
• a first voltage generation circuit electrically connected to the first voltage line, the third voltage line, and the reference voltage line, and configured to generate the third voltage and a first current corresponding to the third voltage;
• a second voltage generation circuit electrically connected to the second voltage line, the fourth voltage line, and the reference voltage line, and configured to generate the fourth voltage;
• a first internal circuit electrically connected to the second voltage line and the reference voltage line;
• and
• a first interface circuit electrically connected to the fourth voltage line, the reference voltage line, and the first internal circuit;
• and
• a semiconductor device including:
• a third voltage generation circuit electrically connected to the first voltage line, the third voltage line, and the reference voltage line, and configured to generate the third voltage and a second current corresponding to the third voltage;
• a memory unit electrically connected to the first voltage line and the reference voltage line;
• a second internal circuit electrically connected to the third voltage line and the reference voltage line;
• and
• a second interface circuit electrically connected to the fourth voltage line, the reference voltage line, the second internal circuit, and the first interface circuit, wherein
• the control circuit is configured to adjust a ratio between the first current supplied from the first voltage generation circuit to the third voltage line and the second current supplied from the third voltage generation circuit to the third voltage line and the second internal circuit.