Read techniques for improving performance in multi-bit memory cells

A memory device, comprising:

• a memory block that includes an array of memory cells that are arranged in a plurality of word lines, a selected word line of a plurality of word lines being programmed according to a storage scheme that includes at least three data states;
• circuitry for reading the data of the selected word line, the circuitry being configured to;
• during a sensing operation, for a set duration, discharge a sensing capacitor through a selected NAND string that includes a selected memory cell to be read,
• after discharging the sensing capacitor for the set duration, conduct a first comparison of a voltage at a sense node to a trip voltage, and
• apply a first voltage to an opposite side of the sensing capacitor from the sense node, and then conduct a second comparison of the voltage at the sense node to the trip voltage.

A computing system, comprising:

• a processing unit;
• a plurality of memory packages in electrical communication with the processing unit;
• each of the memory packages including at least one memory block that includes an array of memory cells that are arranged in a plurality of word lines, a selected word line of a plurality of word lines being programmed according to a storage scheme that includes at least three data states;
• and
• each of the memory packages including sensing circuitry for reading the data of the selected word line, the sensing circuitry being configured to;
• during a sensing operation, for a set duration, discharge a sensing capacitor through a selected NAND string that includes a selected memory cell to be read,
• after discharging the sensing capacitor for the set duration, conduct a first comparison of a voltage at a sense node to a trip voltage, and
• apply a first voltage to an opposite side of the sensing capacitor from the sense node, and then conduct a second comparison of the voltage at the sense node to the trip voltage.