Sub-block mode erase techniques in a memory device

A memory device, comprising:

• a memory block that includes an array of memory cells that are arranged in a plurality of word lines, the plurality of word lines being sub-divided into a plurality of sub-blocks, the plurality of sub-blocks including a first sub-block and a second sub-block;
• circuitry for erasing the memory cells of the memory block, the circuitry being configured to;
• receive instructions to perform an erase operation on the second sub-block,
• determine whether the first sub-block is at least partially programmed,
• set pass voltages for the word lines of the first sub-block based on the determination of whether the first sub-block is at least partially programmed, and
• during at least one erase-verify pulse of the erase operation, apply the pass voltages to the word lines of the first sub-block.

An apparatus, comprising:

• a memory block that includes an array of memory cells that are arranged in a plurality of word lines, the plurality of word lines being sub-divided into a plurality of sub-blocks, the plurality of sub-blocks including a first sub-block and a second sub-block;
• an erasing means for erasing the memory cells of the memory block, the erasing means being configured to;
• receive instructions to perform an erase operation on the second sub-block,
• determine if all of the memory cells the first sub-block are erased or if at least some of the memory cells of the first sub-block are programmed,
• in response to all of the memory cells of the first sub-block being erased, set a pass voltage for the first sub-block at a first pass voltage level,
• in response to at least some of the memory cells of the first sub-block being programmed, set the pass voltage for the first sub-block at a second pass voltage level that is different than the first pass voltage level, and
• during at least one erase-verify pulse of the erase operation, apply the pass voltage to the word lines of the first sub-block.