Managing program disturb in memory devices
AssigneeYangtze Memory Technologies Co., Ltd.
InventorKaikai YOU
Life of this patent
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Abstract
Example memory devices, memory systems, and methods for reducing program disturb in NAND flash memory are disclosed. One example method includes applying, at a first time and during a channel preparation period of a program operation of a first memory cell in a memory cell array, a first voltage to a first word line coupled to the first memory cell. A second voltage is applied to the first word line at a second time after the first time and during the channel preparation period, where the second voltage is lower than the first voltage. A programming voltage is applied to the first word line after the channel preparation period and during the program operation of the first memory cell.
Claims20
A memory device, comprising:
- a memory cell array comprising memory cells;
- and
- a peripheral circuit coupled to the memory cell array and configured to perform operations comprising:
- applying, during a first period of a channel preparation period of a program operation of a first memory cell in the memory cell array, a first voltage to a first word line coupled to the first memory cell;
- applying, during a second period of the channel preparation period, a second voltage to the first word line, wherein the second voltage is lower than the first voltage and the second period is after the first period;
- applying, during the channel preparation period, a select voltage higher than the second voltage to a source select line;
- applying, during the channel preparation period, a first prepare voltage to a second word line, wherein the first prepare voltage is lower than the first voltage;
- and
- applying a programming voltage to the first word line after the channel preparation period and during the program operation of the first memory cell.
A memory system, comprising:
- a memory device, comprising:
- a memory cell array comprising memory cells;
- and
- a peripheral circuit coupled to the memory cell array and configured to perform operations comprising:
- applying, during a first period of a channel preparation period of a program operation of a first memory cell in the memory cell array, a first voltage to a first word line coupled to the first memory cell;
- applying, during a second period of the channel preparation period, a second voltage to the first word line, wherein the second voltage is lower than the first voltage and the second period is after the first period;
- applying, during the channel preparation period, a select voltage higher than the second voltage to a source select line;
- applying, during the channel preparation period, a first prepare voltage to a second word line, wherein the first prepare voltage is lower than the first voltage;
- and
- applying a programming voltage to the first word line after the channel preparation period and during the program operation of the first memory cell.
A method of programming a memory device, comprising:
- applying, during a first period of a channel preparation period of a program operation of a first memory cell in the memory device, a first voltage to a first word line coupled to the first memory cell;
- applying, during a second period of the channel preparation period, a second voltage to the first word line, wherein the second voltage is lower than the first voltage and the second period is after the first period;
- applying, during the channel preparation period, a select voltage higher than the second voltage to a source select line;
- applying, during the channel preparation period, a first prepare voltage to a second word line,
- wherein the first prepare voltage is lower than the first voltage;
- and
- applying a programming voltage to the first word line after the channel preparation period and during the program operation of the first memory cell.
Dependencies are inferred from the claim text.