Memory device with improved programming energy efficiency and reliabilty

A memory device, comprising:

• a memory block including at least one drain-side select gate and an array of memory cells that are arranged in a plurality of word lines;
• circuitry that is configured to program the memory cells of a selected word line in a programming operation, the circuitry being configured to;
• in a programming pulse, apply a select gate voltage VSGD to the at least one drain-side select gate, apply a bit line inhibit voltage VDDSA to a plurality of unselected bit lines, apply a very low voltage to a plurality of selected bit lines, and apply a programming voltage to a selected word line of the plurality of word lines;
• and
• wherein the bit line inhibit voltage VDDSA is no greater than 1.5 V.

A computing system comprising, comprising:

• a processing unit and at least one non-volatile memory package in electrical communication with the processing unit;
• the at least one non-volatile memory package including a memory block with at least one drain-side select gate and an array of memory cells that are arranged in a plurality of word lines;
• circuitry that is configured to program the memory cells of a selected word line in a programming operation, the circuitry being configured to;
• in a programming pulse, apply a select gate voltage VSGD to the at least one drain-side select gate, apply a bit line inhibit voltage VDDSA to a plurality of unselected bit lines, apply a very low voltage to a plurality of selected bit lines, and apply a programming voltage to a selected word line of the plurality of word lines;
• and
• wherein the bit line inhibit voltage VDDSA is no greater than 1.5 V.