Ring oscillator structure to monitor writability of multi-port bitcell

A method of determining writability of multi-port test bitcells in a static RAM (SRAM) of an integrated circuit (IC), comprising:

• initiating a ring oscillator formed from an array of the multi-port test bitcells in the SRAM;
• monitoring oscillations of the ring oscillator for a voltage applied to the array of multi-port test bitcells;
• when the ring oscillator is determined to be oscillating, adjusting the voltage applied to the array of multi-port test bitcells;
• when the ring oscillator is determined to not be oscillating, determining a correlating minimum write voltage to successfully write to the array of multi-port test bitcells;
• and
• sending the correlated minimum write voltage to a register of the SRAM.

A static RAM (SRAM) of an integrated circuit (IC), comprising:

• an array of multi-port bitcells;
• write drivers for the array of multi-port bitcells;
• a decoder for the array of multi-port bitcells;
• control logic for the array of multi-port bitcells;
• and
• a writability monitoring circuit, the writability monitoring circuit comprising:
• a register;
• an array of multi-port test bitcells configured as a ring oscillator;
• and
• control circuitry configured to:
• apply a voltage to the array of multi-port test bitcells;
• determine if the ring oscillator is oscillating;
• when the ring oscillator is determined to be oscillating, adjust the voltage applied to the array of multi-port test bitcells;
• and
• when the ring oscillator is determined to not be oscillating, determine a correlating minimum write voltage to successfully write to the array of multi-port test bitcells and send the correlated minimum write voltage to the register.

A library of circuit designs, comprising:

• a design for a writability monitoring circuit in a static RAM (SRAM) of an integrated circuit (IC), wherein the writability monitoring circuit includes:
• a register;
• an array of multi-port test bitcells configured as a ring oscillator;
• and
• control circuitry configured to:
• apply a voltage to the array of multi-port test bitcells;
• determine if the ring oscillator is oscillating;
• when the ring oscillator is determined to be oscillating, adjust the voltage applied to the array of multi-port test bitcells;
• and
• when the ring oscillator is determined to not be oscillating, determine a correlating minimum write voltage to successfully write to the array of multi-port test bitcells and send the correlated minimum write voltage to the register.

A writability monitoring circuit in a static RAM (SRAM) of an integrated circuit (IC), comprising:

• a register;
• an array of test bitcells configured as a ring oscillator;
• and
• control circuitry configured to determine a correlating minimum write voltage to successfully write to the array of test bitcells and send the correlated minimum write voltage to the register.