Sram architecture for ultra-low array leakage in shut down mode

A method comprising:

• providing a memory device comprising:
• one or more memory cores, wherein each memory core comprises a plurality of column slices of bit cells, and wherein each of the column slices of bit cells comprises a plurality of bit cells;
• one or more footer switch circuitries, wherein each of the one or more footer switch circuitries is associated with a single column slice of bit cells of the plurality of column slices of bit cells, and wherein each of the one or more footer switch circuitries comprises a footer switch;
• wherein each footer switch comprises a footer transistor, wherein each footer transistor comprises a footer transistor drain, a footer transistor gate, and a footer transistor source;
• and
• wherein each footer circuitries is configured with:
• the footer transistor drain of the footer transistor electrically connected to a bit cell source voltage line of a plurality of bit cells and a PWELL region of the associated single column slice of bit cells;
• the footer transistor source of the footer transistor electrically connected to ground;
• and
• the footer transistor gate of the footer transistor configured to receive a shutdown signal to operate, in a shutdown mode, the footer transistor as a switch to electrically connect the bit cell source voltage line of the plurality of bit cells and the PWELL region of the associated single column slice of bit cells with ground;
• receiving a shutdown signal at at least one first footer switch of the plurality of footer switches to operate the at least one first footer switch to connect the bit cell source voltage line of a plurality of bit cells associated with the at least one first footer switch to ground.