Sub-word line driver circuitry including chain of transistors to remove floating word line states

A device comprising:

• a number of word lines, the number of word lines including at least a first word line, a second word line, a third word line, and a fourth word line;
• a number of main word lines;
• a number of sub-word line drivers, each sub-word line driver including a complementary pair of transistors coupled in parallel between a respective main word line of the number of main word lines and a respective word line of the number of word lines, each complementary pair of transistors including an N-type transistor and a P-type transistor;
• a first phase signal line, the first phase signal line coupled to respective gates of respective N-type transistors of respective complementary pairs of transistors of the number of sub-word line drivers;
• a second phase signal line, the second phase signal line coupled to respective gates of respective P-type transistors of the respective complementary pairs of transistors of the number of sub-word line drivers;
• and
• a chain of transistors including:
• a first transistor coupled between the first word line and a voltage line supplied with an inactive voltage;
• a second transistor coupled between the first word line and the second word line;
• a third transistor coupled between the second word line and the third word line;
• and
• a fourth transistor coupled between the third word line and the fourth word line.

A system comprising:

• at least one input device;
• at least one output device;
• at least one processor device operably coupled to the input device and the output device;
• and
• at least one memory device operably coupled to the at least one processor device and including:
• a number of sub-word line drivers, each sub-word line driver including a complementary pair of transistors coupled in parallel between a respective main word line of a number of main word lines and a respective word line of a number of word lines, each complementary pair of transistors including an N-type transistor and a P-type transistor;
• a first phase signal line, the first phase signal line coupled to respective gates of respective N-type transistors of respective complementary pairs of transistors of the number of sub-word line drivers;
• a second phase signal line, the second phase signal line coupled to respective gates of respective P-type transistors of the respective complementary pairs of transistors of the number of sub-word line drivers;
• and
• a chain of transistors, respective transistors of the chain of transistors coupled between respective pairs of word lines of adjacent sub-word line drivers of the number of sub-word line drivers, the chain of transistors including a terminating transistor coupled between a first end word line of the number of word lines and a voltage line supplied with an inactive voltage.