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US 2026/0229276 A1Published application
Memory device generating trimmed bulk voltage for each die
AssigneeSK hynix Inc.
InventorsSe Jun HAN, Tae Ho KIM, Dong Ju YANG, Hyeon Jin YANG
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Abstract
A memory device includes a base die and a plurality of core dies stacked over the base die, each including an internal circuit configured to perform an internal operation and a bulk voltage control circuit configured to generate a bulk voltage. The internal circuit includes at least one MOS transistor configured to operate by receiving the bulk voltage that is adjusted based on an internal temperature of each of the plurality of core dies.
Claims23
A memory device comprising:
- a base die;
- and
- a plurality of core dies stacked over the base die, each comprising an internal circuit configured to perform an internal operation and a bulk voltage control circuit configured to generate a bulk voltage;
- wherein the internal circuit comprises at least one metal oxide semiconductor (MOS) transistor configured to operate by receiving the bulk voltage that is adjusted based on an internal temperature of each of the plurality of core dies.
1 more element
A memory device comprising:
- a first core die stacked over a base die, configured to generate a first bulk voltage at a voltage level that varies based on a first process condition, and configured to supply the first bulk voltage to a body of at least one first metal oxide semiconductor (MOS) transistor included in a first internal circuit;
- and
- a second core die stacked over the first core die, configured to generate a second bulk voltage at a voltage level that varies according to a second process condition, and configured to supply the second bulk voltage to a body of at least one second MOS transistor included in a second internal circuit.
Dependencies are inferred from the claim text.