Access line division for memory devices

A method, comprising:

• activating a word line of a memory array;
• biasing a gate of a transistor based at least in part on whether activating the word line couples a memory cell with a first portion of an access line of the memory array or a second portion of the access line, the first portion of the access line operable to couple with a sense amplifier and the second portion of the access line operable to couple with the first portion via a channel of the transistor;
• and
• sensing, using the sense amplifier, a state of the memory cell based at least in part on activating the word line and biasing the gate of the transistor.

A memory device, comprising:

• a memory array;
• and
• circuitry coupled with the memory array and configured to cause the memory device to:
• activate a word line of the memory array;
• bias a gate of a transistor based at least in part on whether activating the word line couples a memory cell with a first portion of an access line of the memory array or a second portion of the access line, the first portion of the access line operable to couple with a sense amplifier and the second portion of the access line operable to couple with the first portion via a channel of the transistor;
• and
• sense, using the sense amplifier, a state of the memory cell based at least in part on activating the word line and biasing the gate of the transistor.