Memory device performing refresh operation and operating method thereof

A memory device comprising:

• a refresh control circuit configured to generate an internal refresh signal based on a self-refresh section signal;
• a locking control circuit configured to generate the self-refresh section signal according to a self-refresh entry command and a self-refresh exit command, generate a first extension section signal and a second extension section signal based on the self-refresh section signal, and generate a locking start signal by selecting one of the first extension section signal and the second extension section signal based on operation speed information, the first extension section signal having a variable activation period depending on the internal refresh signal and the second extension section signal having a preset activation period;
• and
• a clock generation circuit configured to generate an internal clock by delaying and fixing an external clock in response to the locking start signal.

An operating method of a memory device, the operating method comprising:

• generating at least one speed signal having a logic level based on operation speed information;
• generating a self-refresh section signal activated by a self-refresh entry command and deactivated by a self-refresh exit command;
• generating an internal refresh signal during an activation period of the self-refresh section signal;
• generating a first extension section signal with a variable activation period depending on the internal refresh signal and a second extension section signal with a preset activation period;
• generating a locking start signal by selecting one of the first extension section signal and the second extension section signal according to the speed signal;
• and
• generating an internal clock by delaying and fixing an external clock in response to the locking start signal.