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US 2026/0229269 A1Published application
Semiconductor device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsShunpei YAMAZAKI, Jun KOYAMA, Kiyoshi KATO
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Abstract
An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.
Claims39
(canceled)
A semiconductor device comprising:
- a first transistor including a first channel formation region;
- a second transistor including a second channel formation region;
- a third transistor including a third channel formation region;
- a first conductive layer configured to be a gate of the first transistor, provided over the first channel formation region;
- a first insulating layer provided over the first conductive layer;
- a second conductive layer provided over the first insulating layer, and configured to be a gate of the second transistor;
- a second insulating layer provided over the second conductive layer, and configured to be a gate insulating layer of the second transistor;
- an oxide semiconductor layer provided over the second insulating layer, and including the second channel formation region;
- and
- a third insulating layer provided over the oxide semiconductor layer,
- wherein the first channel formation region includes a material other than oxide semiconductor,
- wherein the third channel formation region includes a material other than oxide semiconductor,
- wherein one of a source and a drain of the second transistor is electrically connected to the gate of the first transistor,
- wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor,
- wherein the other of the source and the drain of the third transistor is electrically connected to a wiring configured to be supplied with a predetermined potential,
- wherein a gate of the second transistor is electrically connected to a first signal line,
- wherein a gate of the third transistor is electrically connected to a second signal line,
- wherein in plan view, the first conductive layer does not overlap the second channel formation region, and
- wherein in plan view, the first channel formation region of the first transistor sends a current in a direction crossing a channel length direction of the second transistor.
16 more elements
(canceled)
A semiconductor device comprising:
- a first transistor including a first channel formation region;
- a second transistor including a second channel formation region;
- a third transistor including a third channel formation region;
- a first conductive layer configured to be a gate of the first transistor, provided over the first channel formation region;
- a first insulating layer provided over the first conductive layer;
- a second conductive layer provided over the first insulating layer, and configured to be a gate of the second transistor;
- a second insulating layer provided over the second conductive layer, and configured to be a gate insulating layer of the second transistor;
- an oxide semiconductor layer provided over the second insulating layer, and including the second channel formation region;
- and
- a third insulating layer provided over the oxide semiconductor layer,
- wherein the first channel formation region includes a material other than oxide semiconductor,
- wherein the third channel formation region includes a material other than oxide semiconductor,
- wherein one of a source and a drain of the second transistor is electrically connected to the gate of the first transistor,
- wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor,
- wherein the other of the source and the drain of the third transistor is electrically connected to a wiring configured to be supplied with a predetermined potential,
- wherein a gate of the second transistor is electrically connected to a first signal line,
- wherein a gate of the third transistor is electrically connected to a second signal line,
- wherein in plan view, the first conductive layer does not overlap the second channel formation region,
- wherein the second insulating layer has a region in contact with the oxide semiconductor layer, and includes silicon and oxygen,
- wherein the third insulating layer has a region in contact with the oxide semiconductor layer, and includes silicon and oxygen, and
- wherein in plan view, the first channel formation region of the first transistor sends a current in a direction crossing a channel length direction of the second transistor.
18 more elements
(canceled)
A semiconductor device comprising:
- a first transistor including a first channel formation region;
- a second transistor including a second channel formation region;
- a third transistor including a third channel formation region;
- a first conductive layer configured to be a gate of the first transistor, provided over the first channel formation region;
- a first insulating layer provided over the first conductive layer;
- a second conductive layer provided over the first insulating layer, and configured to be a gate of the second transistor;
- a second insulating layer provided over the second conductive layer, and configured to be a gate insulating layer of the second transistor;
- an oxide semiconductor layer provided over the second insulating layer, and including the second channel formation region;
- a third insulating layer provided over the oxide semiconductor layer;
- and
- a third conductive layer provided over the third insulating layer,
- wherein the first channel formation region includes a material other than oxide semiconductor,
- wherein the third channel formation region includes a material other than oxide semiconductor,
- wherein one of a source and a drain of the second transistor is electrically connected to the gate of the first transistor,
- wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor,
- wherein the other of the source and the drain of the third transistor is electrically connected to a wiring configured to be supplied with a predetermined potential,
- wherein a gate of the second transistor is electrically connected to a first signal line,
- wherein a gate of the third transistor is electrically connected to a second signal line,
- wherein in plan view, the first conductive layer does not overlap the second channel formation region,
- wherein the first conductive layer is electrically connected to the oxide semiconductor layer through the third conductive layer,
- wherein in plan view, a maximum length of the oxide semiconductor layer in a channel length direction of the second transistor is larger than a maximum length of the oxide semiconductor layer in a channel width direction of the second transistor,
- wherein in plan view, a maximum length of the third conductive layer in the channel length direction of the second transistor is larger than a maximum length of the third conductive layer in the channel width direction of the second transistor,
- wherein in plan view, a maximum length of the first conductive layer in the channel width direction of the second transistor is larger than a maximum length of a region where the third conductive layer overlaps the first conductive layer in the channel width direction of the second transistor, and
- wherein in plan view, the maximum length of the first conductive layer in the channel width direction of the second transistor is larger than the maximum length of the oxide semiconductor layer in the channel width direction of the second transistor.
21 more elements
A semiconductor device comprising:
- a first transistor including a first channel formation region;
- a second transistor including a second channel formation region;
- a third transistor including a third channel formation region;
- a first conductive layer configured to be a gate of the first transistor, provided over the first channel formation region;
- a first insulating layer provided over the first conductive layer;
- a second conductive layer provided over the first insulating layer, and configured to be a gate of the second transistor;
- a second insulating layer provided over the second conductive layer, and configured to be a gate insulating layer of the second transistor;
- an oxide semiconductor layer provided over the second insulating layer, and including the second channel formation region;
- a third insulating layer provided over the oxide semiconductor layer;
- and
- a third conductive layer provided over the third insulating layer,
- wherein the first channel formation region includes a material other than oxide semiconductor,
- wherein the third channel formation region includes a material other than oxide semiconductor,
- wherein one of a source and a drain of the second transistor is electrically connected to the gate of the first transistor,
- wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor,
- wherein the other of the source and the drain of the third transistor is electrically connected to a wiring configured to be supplied with a predetermined potential,
- wherein a gate of the second transistor is electrically connected to a first signal line,
- wherein a gate of the third transistor is electrically connected to a second signal line,
- wherein in plan view, the first conductive layer does not overlap the second channel formation region,
- wherein the first conductive layer is electrically connected to the oxide semiconductor layer through the third conductive layer,
- wherein in plan view, a maximum length of the oxide semiconductor layer in a channel length direction of the second transistor is larger than a maximum length of the oxide semiconductor layer in a channel width direction of the second transistor,
- wherein in plan view, a maximum length of the third conductive layer in the channel length direction of the second transistor is larger than a maximum length of the third conductive layer in the channel width direction of the second transistor,
- wherein in plan view, a maximum length of the first conductive layer in the channel width direction of the second transistor is larger than a maximum length of a region where the third conductive layer overlaps the first conductive layer in the channel width direction of the second transistor,
- wherein in plan view, the maximum length of the first conductive layer in the channel width direction of the second transistor is larger than the maximum length of the oxide semiconductor layer in the channel width direction of the second transistor,
- wherein the second insulating layer has a region in contact with the oxide semiconductor layer, and includes silicon and oxygen, and
- wherein the third insulating layer has a region in contact with the oxide semiconductor layer, and includes silicon and oxygen.
23 more elements
Dependencies are inferred from the claim text.